NVMe PCIe Bandwidth Calculator
Need to know if your PCIe slot is the bottleneck or your NVMe drive? The NVMe PCIe Bandwidth Calculator compares the slot's theoretical ceiling against your drive's rated throughput. Select your PCIe Generation and Lane Width, enter your NVMe Drive's Rated Sequential Read and Write speeds and the Number of Drives sharing that slot, and you'll see bottleneck identification, slot utilisation percentage, and aggregate bandwidth for multi-drive configurations — plus the full PCIe bandwidth reference table at the bottom.
PCIe Generation, Lane Width and NVMe Drive Selection
Maximum NVMe Sequential Bandwidth at Your PCIe Configuration
PCIe Slot Bandwidth
Drive Peak Read
Slot Utilisation (Read)
Read Bottleneck
| Metric | Read | Write |
|---|---|---|
| PCIe slot bandwidth ceiling | — | — |
| Drive rated (single drive) | — | — |
| Effective throughput (1 drive) | — | — |
| Total rated (N drives) | — | — |
| Effective total (slot-limited) | — | — |
| Slot utilisation | — | — |
| Bottleneck | — | — |
| Bandwidth headroom remaining | — | — |
PCIe Bandwidth Reference — All Generations & Lane Widths
| PCIe Gen | Transfer Rate | Encoding | x1 | x4 (NVMe M.2) | x8 | x16 |
|---|---|---|---|---|---|---|
| PCIe 3.0 | 8 GT/s | 128b/130b | 0.98 GB/s | 3.94 GB/s | 7.88 GB/s | 15.75 GB/s |
| PCIe 4.0 | 16 GT/s | 128b/130b | 1.97 GB/s | 7.88 GB/s | 15.75 GB/s | 31.51 GB/s |
| PCIe 5.0 | 32 GT/s | 128b/130b | 3.94 GB/s | 15.75 GB/s | 31.51 GB/s | 63.01 GB/s |
| PCIe 6.0 | 64 GT/s | FLIT/PAM4 | 7.56 GB/s | 30.25 GB/s | 60.50 GB/s | 121.0 GB/s |
NVMe Drive Performance vs PCIe Slot Requirement
| NVMe Drive Class | Interface | Seq Read (MB/s) | Seq Write (MB/s) | Min PCIe Slot | Slot Utilisation |
|---|---|---|---|---|---|
| Entry NVMe (Gen 3) | PCIe 3.0 x4 | 2,400 | 1,800 | PCIe 3.0 x4 | ~61% |
| Mid-range NVMe (Gen 3) | PCIe 3.0 x4 | 3,500 | 3,300 | PCIe 3.0 x4 | ~89% |
| High-end NVMe (Gen 4) | PCIe 4.0 x4 | 7,400 | 6,500 | PCIe 4.0 x4 | ~94% |
| Enterprise NVMe (Gen 4) | PCIe 4.0 x4 | 6,900 | 4,100 | PCIe 4.0 x4 | ~88% |
| Consumer NVMe (Gen 5) | PCIe 5.0 x4 | 14,500 | 12,700 | PCIe 5.0 x4 | ~92% |
| Enterprise NVMe (Gen 5) | PCIe 5.0 x4 | 13,000 | 8,000 | PCIe 5.0 x4 | ~83% |
Slot utilisation = drive sequential read ÷ PCIe slot bandwidth × 100. Values above 95% indicate the slot is very close to being the bottleneck.
How PCIe Gen 3, 4 and 5 Affect NVMe Drive Speed and Bottlenecks
NVMe (Non-Volatile Memory Express) storage performance is fundamentally bound by two ceilings: the NVMe drive's own rated throughput and the PCIe slot bandwidth available to it. Unlike SATA SSDs that are always limited by the 600 MB/s SATA interface, NVMe drives can only reach their full sequential throughput when the PCIe slot provides enough bandwidth. Understanding whether your PCIe generation, lane width, or drive specification is the actual bottleneck is essential for server storage design, workstation builds, HPC storage arrays, and any environment where you are paying a premium for NVMe PCIe Gen 4 or Gen 5 drives and need to verify the system delivers the advertised performance. Related: Calculate optimal NVMe queue depth for peak IOPS.
PCIe bandwidth scales with two variables: generation and lane width. Each successive PCIe generation doubles the per-lane bandwidth — PCIe 3.0 delivers 984 MB/s per lane, PCIe 4.0 delivers 1,969 MB/s per lane, PCIe 5.0 delivers 3,938 MB/s per lane, and PCIe 6.0 delivers 7,563 MB/s per lane using PAM4 signalling and FLIT encoding. An NVMe M.2 drive uses a PCIe x4 slot by default: PCIe 3.0 x4 = 3.94 GB/s, PCIe 4.0 x4 = 7.88 GB/s, PCIe 5.0 x4 = 15.75 GB/s. A top-spec PCIe Gen 5 x4 NVMe drive rated at 14 GB/s sequential read fits comfortably in a PCIe 5.0 x4 slot but would be severely bottlenecked in a PCIe 3.0 x4 slot — limited to 3.94 GB/s regardless of the drive's capability. Check out our estimate NVMe drive IOPS and throughput.
PCIe bifurcation allows a single physical PCIe x16 slot to be split into multiple narrower slots — for example, x16 bifurcated as x4x4x4x4 — enabling NVMe RAID controllers or PCIe switch cards to host multiple NVMe drives on a single slot. When designing multi-drive NVMe configurations, the aggregate throughput of all drives must not exceed the total PCIe slot bandwidth or the upstream PCIe root complex bandwidth. A server with four PCIe Gen 4 x4 NVMe drives each rated at 7 GB/s requires 28 GB/s of PCIe bandwidth — which fits in a single PCIe Gen 4 x16 slot (31.5 GB/s) but would require two PCIe Gen 3 x16 slots (15.75 GB/s each). The NVMe PCIe bandwidth calculator on this page solves exactly this planning problem, showing both per-drive and aggregate bottleneck analysis instantly. You might also need: calculate NVMe SSD endurance and lifespan.
x4, x8, x16 Lanes, PCIe Bifurcation and M.2 vs U.2 Explained
PCIe Bandwidth Calculation: PCIe uses 128b/130b encoding (Gen 3/4/5) meaning 128 data bits per 130 transmitted bits — approximately 98.5% efficiency. Bandwidth = Transfer_Rate × Lanes × (128/130) / 8 bytes.
PCIe 6.0 FLIT Encoding: PCIe 6.0 switches from 128b/130b to FLIT (flow control unit) mode with PAM4 signalling, achieving ~94% efficiency at 64 GT/s per lane. This doubles bandwidth over Gen 5 at the same lane count.
PCIe Bifurcation: A PCIe x16 slot can be split into multiple narrower connections — e.g., x16 → x8+x8, or x16 → x4+x4+x4+x4. An NVMe RAID card or PLX switch uses bifurcation to host multiple NVMe drives on one physical slot. Must be enabled in BIOS/UEFI.
NVMe M.2 vs U.2 vs E1.S: M.2 NVMe uses PCIe x4. U.2 (2.5" enterprise) also uses PCIe x4 but with a different connector. E1.S and EDSFF drives use PCIe x4 or x8 and are designed for dense server storage. All follow the same PCIe bandwidth rules.
Backwards Compatibility: PCIe is backwards-compatible — a Gen 4 NVMe drive in a Gen 3 slot runs at Gen 3 speeds (lower bandwidth). Always match or exceed the drive's PCIe generation requirement at the slot for full performance.
CPU vs Chipset Lanes: CPU-direct PCIe lanes have lower latency than chipset PCIe lanes. On modern platforms, M.2 slots wired directly to the CPU (typically slots 0 and 1) offer lower latency than chipset-connected M.2 slots, even at the same PCIe generation.